1. Field of the Invention
The present invention relates generally to a semiconductor memory device, more specifically, to a static random access memory (hereinafter referred to as SRAM).
2. Description of the Related Art
Recently, storage capacities of a semiconductor memory devices have increased to such a extent that memory devices no longer require the size they once needed to perform a particular function. To further increase the memory capacity and to decrease the dimensional size of semiconductor memory devices, a reduction of the number of bit lines in cell arrays is herewith proposed by the following invention.
FIG. 1 illustrates a first conventional device of SRAM. A plurality of memory cells C00 through Cmn are coupled via switching elements SW000 through SW1mn, to multiple pairs of bit and bar bit lines, BL0 through BLm and bar BL0 through BLm, respectively. Memory cells C00 through Cmn are formed using a latch circuit with two CMOS invertor circuits as memory cell elements. Each of the switching elements SW000 through SW1mn is constructed with a n-channel MOS transistor, and is coupled to one of the word lines WL0 through Wln. When any one word line is selected by a decoder, and the state of the selected word line goes high, the switching element coupled to the selected word line is switched to the ON state. Following this, a memory cell coupled to the activated switching element is selected, and data is read or written from or to the selected memory cell via one from bit lines BL0 and bar BL0 through BLm and bar BLm.
According to the above-described SRAM, a pair of bit lines is provided to a series of memory cells. Therefore, the number of bit lines increases in proportion to the increase in the number of cell arrays. With the large scale cell arrays manufactured today, design constraints require increasingly larger areas for bit line layout. In an attempt to decrease the number of the bit lines, a SRAM having a structure shown in FIG. 2 has been proposed, wherein the previous and adjacent bit lines shown separated as in FIG. 1, are combined to one common bit line.
However, there are disadvantages of using such types of SRAM when reading and writing data from or to adjacently disposed memory cells, e.g., from cells C00, C10 coupled to the common word line WL0. For example, if the word line WL0 is selected during a time when data is stored in the memory cells C00, C10, and in a case where an output from one of two memory cells connected to a common bit line is high and an cell C10 to the cell C00 as shown in FIG. 2. This causes the state of the bit line bar BL1, between both cells C00 and C10, to be intermediately biased between high and low voltage states, which in turn results in a condition where the data stored in memory can not be accurately read.
To solve the above-described drawbacks, Japanese Unexamined Patent Publication Nos. 63-42093 and 3-259495 disclose SRAMs in which clamp circuits are provided to the bit lines in order to suppress variations in bit line voltage potential.
Further, Japanese Unexamined Patent Publication No. 3-76095 discloses a SRAM, in which each of the adjacent memory cells is selected by a separate word line in order to reduce the interference between adjacent memory cells. This construction, however, causes an accompanying decrease in memory cell access time. Also, the variation in the range of voltage potential for circuitry using such bit lines is reduced, making it more likely that noise inherent to the circuit would exceed the circuit's threshold noise level. This bit line construction, thus, creates a tendency for the circuit to be overly effected by noise. Finally, with the SRAM disclosed in Japanese Unexamined Patent Publication No. 3-76095, as the number of word lines increases, the advantage of combining bit lines to reduce the layout area is diminished by the additional space needed for the increased number of word lines.